File:Verilog Circular Assignment.svg
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| Description |
English: A circular assignment in Verilog:
wire a, b; assign a = a | b;In this case, the value of the wire a is undefined, because it is fed by itself through combinational logic. |
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| Date | |||
| Source | Own work | ||
| Author | Inductiveload | ||
| Permission (Reusing this file) |
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 00:27, 23 May 2009 | | 125 × 100 (7 KB) | Inductiveload | {{Information |Description={{en|1=A circular assignment in Verilog: wire a, b; assign a = a | b; In this case, the value of the wire <tt>a</tt> is undefined, because it is fed by itself through combinational logic. }} |Source=Own work by uploader |Auth |
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