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File:Verilog Simple Assignment.svg

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Description
English: A simple assignment in Verilog 
wire a, b, c;
assign a = b & c;
Date
Source Own work
Author Inductiveload
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Public domain I, the copyright holder of this work, release this work into the public domain. This applies worldwide.
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I grant anyone the right to use this work for any purpose, without any conditions, unless such conditions are required by law.

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inception

23 May 2009

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current00:34, 23 May 2009Thumbnail for version as of 00:34, 23 May 2009125 × 70 (10 KB)Inductiveload{{Information |Description={{en|1=A simple assignment in Verilog wire a, b, c; assign a = b & c;}} |Source=Own work by uploader |Author=Inductiveload |Date=2009/05/23 |Permission={{PD-self}} |other_versions= }} <!--{{ImageUpload

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