360 Assembly/360 Instructions/BCTR

BC - Branch on Count - RX type instruction - Opcode 46

Format

 BCTR 2,4
 BCTR 15,3
 BCTR 7,8
 BCTR 1,0 - Value in register 1 is decremented, but no branch will occur

Opcode

RR Instruction (2 bytes)
	Byte 1 bits (0-7)	Byte 2
		target register (8-11)	branch register (12-15)
(in hex)	Opcode 06	(4 bits) 0..F / (dec 0..15)	(4 bits) 0..F / (dec 0..15)

• The first argument is a target register which value is affected by the instruction.
• The second argument is the branch register whose contents are to be used as the location to transfer to (if the argument is not zero).
• The target register and branch register values are 0 to 15.

Example usage

BCTR 1,9

Availability

The BCTR instruction is available on all models.

Purpose of Instruction

The BCTR instruction subtracts 1 from the value of the contents of the target register specified in the first argument. If the value in the target register after the subtraction is zero (or the branch register is 0), no branch occurs. Otherwise the program branches to the address contained in the branch register specified in the second argument. Note that if the result in the target register before subtraction is 0, the result is negative 1 and the branch occurs (unless the branch register is 0). If the value in the target register is the lowest possible value, the overflow that occurs is ignored, the result in the target register is the highest possible value, and the branch occurs (unless the branch register is 0). A BCTR 0,0 instruction is the equivalent of decrementing register 0 by 1.

Typical Usage

To do a loop statement where 1 is subtracted from the value contained in the target register, and a branch should occur to the address contained in the branch register if the result isn't 0.

Operation

The value contained in the register specified as the first argument is reduced by 1. If the branch register is 0, or the value after subtraction of the value in the target register is 0, execution continues with the instruction following this instruction. Otherwise, execution transfers to the address contained in the register specified as the second argument.

Condition Codes

Condition codes are not changed. If the value is the lowest possible value and overflow to the highest value occurs, it is ignored.

Exceptions and Faults

• The target address contained within the branch register must not be odd, or an operation exception occurs
• The target address contained within the branch register must be within the range of valid memory or an operation exception occurs.
• The storage key for the target address must be the same as the current process (or this process must have a key of 0) or a memory protect violate exception occurs.

Alternative branch instructions

• The BCT instruction provides the same functionality but with the branch address specified in Indexed Base-Displacement format.

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