360 Assembly/360 Instructions/L

L - Load - Opcode 58 - RX format Instruction (32-bit)

Format

L 2,N2

L 11,106(8,10)

The specific syntax is

L target register,offset(index register,base register)

where the offset, index register, and base register values are determined automatically by the assembler if the USING pseudo-instruction is used and the target address label used is within 4096 bytes of the value of some base register.

Opcode

RX Instruction (4 bytes)
	Byte 1	Byte 2		Bytes 3 and 4
		target register	Source Address
(In Hex)	(8 bits) Opcode 58	(4 bits) 0..F	(4 bits) index register 0..F	(4 bits) base register 0..F	(12 bits) displacement 0..FFF

• The first argument is a target register which value is affected by the instruction.
• The second argument is the source value location address where the contents are to be loaded into the target register. This consists of a base register, an index register, and a displacement address. The displacement is used as an unsigned offset of 0 to 4095 from the value in the base register, and this displacement is added to the value contained in the base register. If the index register is 0, it is ignored; otherwise, its contents are added to the previous result to obtain the final address.
• The base_register and index_register values are 0 to 15. The offset address is 0 to 4095.

The target and base_register values will be determined automatically by the assembler if the USING pseudo-instruction has been used, and the target address label used (the displacement) is within 4096 bytes of the value of some base register.

Availability

The L instruction is available on all models of the 360, 370 and z/System.

Operation

The L instruction reads a 32-bit integer value from the memory address specified by the argument and puts it to the register specified by the first argument. The high bits of a 64-bit register are unchanged.

The source argument address shall be aligned to word boundary (i.e. 4 bytes). The Condition Code field in the Program Status Word is not changed.

Exceptions and Faults

• The source address must be within the range of valid memory or an operation exception occurs.
• The source address must be aligned to a word boundary or an address exception occurs.
• The storage key for the source address must be such that the location is readable by the current process (or the process must be privileged with a key of zero) or a memory protect violate exception occurs.

Most Closely-related Instruction

The most closely-related instruction is Add Logical Register (ALR) and not Load Address (LA), as is sometimes assumed. Whereas L loads a value from memory, LA does not access memory; it only calculates a number, which can but does not have to be an address.

32-Bit Instructions

• To load an 8-bit byte (character) value from memory, see IC.
• To load one or more 8-bit byte values into a register according to a mask, see ICM
• To load a 16-bit half-word value from memory, see LH.
• To load a 12-bit unsigned value into a register or add up to 4095 to the values in one or two 32-bit registers, see LA.
• To copy a 32-bit word value from one register to another register, see LR.
• To load a 32-bit word value from memory, see L.
• To store an 8-bit byte (character) value in memory, see STC.
• To store one or more 8-bit byte values into memory according to a mask, see STCM
• To store a 16-bit half-word value in memory, see STH.
• To store a 32-bit word value in memory, see ST.

64-Bit Instructions

• To load a 20-bit signed value into a 32-bit or 64-bit register from an extended (20-bit) signed memory offset, see LAY.
• To load a 32-bit value into a 64-bit register from an extended (20-bit) signed memory offset, see LGF.
• To copy a 64-bit value from one 64-bit register to another 64-bit register, see LGR.
• To load a 64-bit value into a 64-bit register from memory, see LG.
• To store a 32-bit value from a register to an extended (20-bit) signed memory offset, see STY.
• To store a 64-bit value from a 64-bit register to an address in memory, see STG.

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