Embedded Systems/ARM Instructions

ARM Instruction Set Format

Instruction Type	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Branch and Branch with Link	Cond				1	0	1	L	24-bit signed word offset
Branch and Branch with Link and eXchange	Cond				0	0	0	1	0	0	1	0	1	1	1	1	1	1	1	1	1	1	1	1	0	0	L	1	Rm
	1	1	1	1	1	0	1	H	24-bit signed word offset
Software Interrupt (SWI)	Cond				1	1	1	1	24-bit (interpreted) immediate
Data Processing Instructions	Cond				0	0	I	opcode				S	Rn				Rd				operand2
Multiply Instructions	Cond				0	0	0	0	mul			S	Rd/RdHi				Rn/RdLo				Rs				1	0	0	1	Rm
Count Leading Zeros	Cond				0	0	0	1	0	1	1	0	0	0	0	0	Rd				0	0	0	0	0	0	0	1	Rm
Data Transfer Instructions	Cond				0	1	I	P	U	B	W	L	Rn				Rd				operand2
	Cond				0	0	0	P	U	I	W	L	Rn				Rd				offsetH				1	S	H	1	offsetL
Multiple Register Transfer Instructions	Cond				1	0	0	P	U	S	W	L	Rn				register list
Swap Memory and Register Instruction	Cond				0	0	0	1	0	B	0	0	Rn				Rd				0	0	0	0	1	0	0	1	Rm
Status Register <=> General Register Transfer Instructions	Cond				0	0	0	1	0	R	0	0	1	1	1	1	Rd				0	0	0	0	0	0	0	0	0	0	0	0
	Cond				0	0	I	1	0	R	1	0	field				1	1	1	1	operand
Coprocessor Data Operations	Cond				1	1	1	0	Cop1				CRn				CRd				CP#				Cop2			0	CRm
Coprocessor Data Transfers	Cond				1	1	0	P	U	N	W	L	Rn				CRd				CP#				8-bit offset
Coprocessor Register Transfers	Cond				1	1	1	0	Cop1			L	CRn				Rd				CP#				Cop2			1	CRm
Breakpoint Instruction	1	1	1	0	0	0	0	1	0	0	1	0	x	x	x	x	x	x	x	x	x	x	x	x	0	1	1	1	x	x	x	x

We go into more detail on how to use ARM instructions in ARM Microprocessors.