Oberon/V5

Installing

For installation on FPGA machines, refer to the documentation of N. Wirth and of P. Reed. Oberon RISC Emulators work on contemporary MS Windows, Unix-like systems and macOS. Refer to instructions of the author of the emulator of interest. Additional notes are available for Android. On some machines the size of block random access memory (BRAM) may constrain development objectives.

Text

Compare with Text in V2.

The Type Text

Type	Fields of TextDesc	Types of Fields	Notes
Texts.Text, a pointer to a Texts.TextDesc	len	INTEGER	Length of text, in bytes.
	changed	BOOLEAN	Flag indicating a revision.
	notify	Texts.Notifier	Pointer to a method to notify interested clients of state changes.
	trailer	Texts.Piece	Pointer to the Sentinel node in the list of pieces.
	pce	Texts.Piece	Last found piece.
	org	INTEGER	Offset in [0,len) of first character in last found piece.

Texts.Piece

Type	Fields of PieceDesc	Types of Fields	Notes
Texts.Piece, a pointer to a Texts.PieceDesc	f	Files.File	Pointer, to file.
	off	INTEGER	Integer offset in Text of first character in Piece.
	len	INTEGER	Number of bytes in Piece.
	fnt	Fonts.Font	Pointer to a font.
	col	INTEGER
	voff	INTEGER	Vertical offset of characters in pixels.
	prev	Texts.Piece	Pointer to previous piece of Text.
	next	Texts.Piece	Pointer to next piece of Text.

Notes

Fixup

Compilation of a module produces branches in which addresses are relative to the base of the module. Fixup is the conversion of these addresses to absolute addresses. Extended Oberon has obviated fixup in the symbol file; not in the fixup lists of an object file.

Refer to Project Oberon (New Edition 2013). Fixup is performed by the module loader, Modules.Load, as discussed in section 6.1. Linking and loading, page 79. Also refer to the mailing list at 2019-11-18 and at 2020-12-16..18.

In section "6.3. The linking loader" is the paragraph beginning "At the very end of the file three integers called fixorgP, fixorgD, and fixorgT are read."
a) A search for "fixorgP" in the code generator module ORG will find this line in ORG.Call.

Put3(BL, 7, ((-x.r) * 100H + x.a) * 1000H + pc-fixorgP); fixorgP := pc-1

Also, this line is in ORG.Put3.

code[pc] := ((op+12) * 10H + cond) * 1000000H + (off MOD 1000000H); INC(pc)

b) -x.r in an item x for a procedure is the module number, mno, and x.a is the entry number for the procedure, pno.

c) From ORG.Call and ORG.Put3 deduce,

the 4 bits [20..23]  = -x.r (= the module number, mno)
the 8 bits [12..19]  =  x.a (= the entry number for the procedure, pno) 
the 12 bits [0..11]  =  pc-fixorgP (= the displacement between 2 instructions in the fixup chain)

With steps (a-c) the compiler generates this instruction precursor.

| BL (4) | cond (4) | mno (4) | pno (8) | pc-fixorgP (12) |

The precursor is not formatted as an instruction but is the same length as one, 32 bits.

d) The lines of (c) correspond to these lines in Modules.Load.

mno := inst DIV 100000H MOD 10H;
pno := inst DIV 1000H MOD 100H;
disp := inst MOD 1000H;

Modules.Load converts the precursor to the second (u=1) F3 format of RISC-Arch.pdf section 3.

| BL (4) | cond (4) | offset relative to PC (24) |

Sources

Published V5	Variant	Notes
Files.Mod
	Out.Mod	Allow delay of execution of Append, using a flag variable.
	Out1.Mod	Allow delay of execution of Append, using a procedure variable.
Texts.Mod