Jump to content

Z80 Assembly/Z80 Architecture

From Wikibooks, open books for an open world

The Z80 architecture is based on that of the Intel 8080.

Registers

[edit | edit source]

The Z80 has eight main registers, six of which are paired to form three 16-bit general-purpose registers.

  • A (accumulator) is the main 8-bit general-purpose register.
  • F (flags) stores flags used to control the flow of a program that are set based on the last arithmetic instruction:
    • Bit 7 (S; sign bit) indicates whether the result was negative.
    • Bit 6 (Z; zero bit) indicates whether the result was zero.
    • Bit 4 (H; half-carry bit) indicates whether the result required a carry from a lower to an upper nybble.
    • Bit 2 (P; parity bit) indicates the parity of the result.
    • Bit 1 (N; subtraction bit) indicates whether the operation was a subtraction.
    • Bit 0 (C; carry bit) indicates whether a carry occurred.
  • BC is a 16-bit register, made up of B (most significant byte) and C (least significant byte).
  • DE is a 16-bit register, made up of D (most significant byte) and E (least significant byte).
  • HL is a 16-bit register, made up of H (most significant byte) and L (least significant byte). HL is generally used for addressing locations in memory, as there are a number of instructions that use HL for this purpose that don't have counterparts for BC and DE.

Each of these main registers has a shadow register counterpart. These registers are accessed by swapping with the main registers using the EX and EXX instructions. EX can be used to swap A and F with their shadow counterparts A' and F', while EXX swaps the three pairs BC, DE, HL with their counterparts BC', DE', HL'.

In addition to the 8-bit registers there are a number of special 16-bit registers:

  • IX and IY are the index registers, designed to be used as base offsets for addressing memory.
  • PC is the program counter, indicating the location of the currently executing instruction.
  • SP is the stack pointer, indicating the location of the top of the processor stack.